Embodiments of the invention relate generally to structures and methods for packaging electrical components and, more particularly, to an electronics package and associated method of manufacture that provides self-alignment of the electrical component(s) to a pre-tested interconnect assembly.
As semiconductor device packages have become increasingly smaller and yield better operating performance, packaging technology has correspondingly evolved from leaded packaging, to laminated-based ball grid array (BGA) packaging, to chip scale packaging (CSP), then flip chip packages, and now buried die/embedded chip build-up (ECBU) packaging. Advancements in semiconductor chip packaging technology are driven by ever-increasing needs for achieving better performance, greater miniaturization, and higher reliability. New packaging technology has to further provide for the possibilities of batch production for the purpose of large-scale manufacturing thereby allowing economy of scale.
A standard embedded device manufacturing process typically begins with coating a top surface of a mounting substrate with an adhesive and placing one or more semiconductor dies or chips into the adhesive. A plurality of re-distribution layers are then deposited onto the mounting substrate and the die(s) and are patterned to form a thin-film metal re-routing and interconnection system, with eight or more re-distribution layers being common. The re-distribution layers are typically formed from a benzocyclobutene (BCB) or polyimide material, for example, and applied via a spin-on or lamination application process. The electrical connection between the laminate re-distribution layers and the die(s) form an input/output (I/O) system to and from the die(s).
Advancements in IC packaging requirements pose challenges to the existing embedded chip build-up process. In order to manufacture smaller and more complex IC packages, dies must be positioned more closely together and with great precision on the dielectric. However, the adhesive layer that couples the dies to the dielectric can make precise alignment of closely spaced dies difficult. For example, when two or more dies are positioned in close proximity to one another on the dielectric, the dies have a tendency to “swim” or move out of the desired position during the adhesive curing process. In addition to merely moving out of the desired position, closely spaced dies may be attracted to one another while the adhesive is curing, a phenomenon that may cause the undesired result of dies touching or becoming stuck to one another in the final electronics package.
Additionally, in order to meet the continued demand for smaller and more complex IC packages, highly complex interconnect structures are integrated within embedded packages to form the electrical connections between embedded electrical components and package I/Os. These complex interconnect structures carry with them inherent yield losses resulting from processing defects such as electrical shorts and/or opens. These defects become more prevalent as line widths, line spacing, and via diameters are reduced as device I/O count increases. In conventional flip chip or wire bonded chip carrier assemblies, the interconnect structure is fully fabricated and electrically tested prior to assembling a costly chip. Thus, a defective interconnect structure does not cause the loss of a costly chip. The interconnect structure in embedded packaging techniques, on the other hand, is fabricated after the electronic devices have been incorporated into the structure, potentially causing a good chip to be scrapped with a bad package.
Accordingly, it would be desirable to provide a new electrical package structure and associated manufacturing process that can provide the advantages of an embedded chip module without the costly loss of a good electrical component due to a defective interconnect structure. There is a further need for a simplified method for fabricating an electronics package that allows for precise die alignment and closer die spacing within the IC package.